Three-dimensional semiconductor packages become essential for a higher density and capacity. The 3D semiconductor packaging technology is by thinning semiconductor chips, and stacking them in multilayer structure while providing through-silicon via (TSV) interconnects. Fabrication of such packages requires the steps of thinning a substrate having a semiconductor circuit formed therein by grinding its non-circuit forming surface or back surface, and forming TSV and electrodes on the back surface. In the prior art, prior to the step of grinding the back surface of a silicon substrate, a protective tape is attached to the surface of the substrate opposite to the surface to be ground for preventing the wafer from breakage during the grinding step. Since the protective tape is based on an organic resin film, it is flexible, but has insufficient strength and heat resistance to withstand the TSV forming step and the step of forming interconnects on the back surface.
It is then proposed to bond a semiconductor substrate to a support of silicon or glass, for example, via an adhesive layer. The resulting system is sufficient to withstand the steps of grinding the back surface and forming TSV and electrodes on the back surface. See Patent Documents 1 and 2. Although the TSV-related technology is expected as the technology for high density interconnection between chips, especially the technology for connecting a wide band memory to a processor, it is now applied only to some limited applications because of expensiveness.
Recent attention is paid to the fan-out wafer level package (FOWLP) technology as described in Patent Document 3. The FOWLP is a package of the structure that an insulated fine redistribution layer (RDL) is formed on an IC chip so as to be fanned out of the chip area. This package achieves high-density wiring between a plurality of chips and substantial reductions in size and profile over conventional packages.
Among others, a study is made on the RDL-first technique involving direct processing of RDL formation on a support substrate, placement of device chips, and resin encapsulation, in order to improve the accuracy of alignment of RDL with chips and to be applied to an application processor having numerous terminals. RDL formation and packaging must be followed by release of the support substrate. Since this technique is different from the sequence of once bonding a support substrate to a semiconductor substrate and machining the back surface of the semiconductor substrate, the adhesive system used in the TSV forming technology fails to comply with this technique.
Under the circumstances, Patent Document 4 discloses a structure including a release layer containing a laser-decomposable resin on a support. In this case, a RDL is formed directly on the release layer. If the release layer remaining on the RDL after the release of the support by laser irradiation is formed of a thermoplastic resin which can be cleaned with a solvent, the release layer can be deformed under high-temperature conditions under which the insulating layer is cured prior to formation of RDL, and hence, metal wiring can also be deformed. On the other hand, if the release layer is formed of a thermosetting resin, heat resistance is improved, but the cured release layer is left on the RDL after release of the support following laser irradiation, which is difficult to remove by solvent cleaning.